Indicative contents
1. Creating design libraries and adding data
2. Detail design of Partitioning, FloorPlanning and PowerPlanning
for both hierarchical and flatten netlist
3. Design timing analysis and correction
4. Detail Design Placement and optimization
5. Clock Tree synthesis (CTS) and Clock tree optimization (CTO)
6. Routing and Post routing optimization
7. Parasitic extraction
8. Design for Manufacturability (DFM)
9. Physical Verification (DRC,LVS)
10. Considering the above flow and methodology need to implement the
case studies from RTL to GDSII.
The case studies are categorized as follows:
- Combinational Design
1. Pipelined 8-bit Multiplier
2. Adder/Subtractor
3. ALU
4. Signed Divider
- Sequential Designs
1. Gray Counter
2. LFSR
3. Up/Down Counter
4. CRC
5. FIR Filter
- Finite State Machine Design
1. Sequence Detector
2. Traffic Light Controller
- Memory Design
1. Dual Port RAM
- Multiple Clock Domains
1. Asynchronous FIFO
2. Real Time digital clock
Module Resources
- Books
- Sadiq M. Sait and Habib Youssef, VLSI Physical Design
Automation: Theory and Practice, IEEE Press.
- Sadiq M. Sait and H. Youssef, VLSI Physical Design
Automation: Theory and Practice, World Scientific, 1999.
- M. Sarrafzadeh and C. K. Wong, An Introduction to VLSI
Physical Design, McGraw Hill Publications, 1996.
- Digital Integrated Circuits: A Design Perspective (2nd Ed.),
J. M. Rabaey, A. Chandrakasan, B. Nikolic (Prentice-Hall, 2003)
- Algorithms for VLSI Physical Design Automation, N. A.
Sherwani (Kluwer Academic Publisher, 1993)
- Introduction to Algorithms (2nd Ed.), Cormen, Leiserson,
Rivest, and Stein (MIT Press, 2001).
- Laboratory
Software Tools / Hardware : Astro, Physical Compiler,
Hercules, Jupiter, St-RCXT, Prime Time, Soc_encounter, Assura DRC,
and Assura LVS
Lab Manuals : Astro (MSRSAS), Physical Compiler
(MSRSAS) , Hercules (MSRSAS) , Jupiter (MSRSAS) , St-RCXT
(MSRSAS) , Prime Time (MSRSAS), Soc_encounter (MSRSAS), Assura
DRC, and Assura LVS (MSRSAS)
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