Indicative contents

• Introduction to ASIC Design Methodology
  1. ASIC Design overview.
  2. Introduction to the ASIC design flow
  3. Overview of EDA tools for ASIC design
• Logic Synthesis and Optimization Techniques
  1. Introduction to Logic synthesis and Synthesis issues
  2. RTL Coding Guidelines for efficient Synthesis
  3. Libraries and Design Rule Constraints
  4. Synthesis Process
  5. Constraint and Optimization
• Timing Analysis in ASIC’s
  1. Overview of Timing
  2. Definition of Setup time, Hold time, Slack, Metastability.
  3. Timing Paths, Critical path and path groups
  4. Timing Exceptions
  5. Clock skew, Multiple clocks.
  6. Delay Calculation, Cell Delay, Net Delay
  7. Dynamic timing analysis and Static timing analysis.
  8. Pre layout and post layout STA.
  9. Timing Models
• VLSI Testing
  1. Introduction to VLSI Testing
  2. Fault Modeling and Fault Simulation
  3. Testing of Combinational circuits
  4. Exhaustive test generation
  5. Algebraic (symbolic) techniques
  6. Path-oriented techniques
  7. Testing sequential circuits
  8. Digital DFT and Scan Design
  9. Need for Design for Testability
  10. Ad Hoc DFT Guidelines
  11. Design a circuit for guaranteed test generation
  12. Scan design approaches
   

Module Resources

• Essential reading
  1. Course notes
• Recommended Reading
  1. Smith, Michael John Sebastian - Application - Specific Integrated Circuits – Pearson 1997.
  2. Micheli, Giovanni - Synthesis and Optimization of Digital Circuits – Tata Mc Graw Hill 2005.
  3. Himanshu Bhatnagar - Advanced Asic Chip Synthesis Using Synopsys Design Compiler Physical and PrimeTime – Kluwer 2002.
  4. Pran Kurup, Pran, Abbasi, Taber - Logic Synthesis Using Synopsys – Kluwer 1997.
  5. Sabih Gerez - Algorithms for VLSI Design Automation – John Wiley 1998.
  6. Horspool, Nigel, Gorman, Peter - ASIC Handbook – Prentice Hall 2001.
  7. Gebotys, Catherine H, Elmasry, Mohamed - Optimal VLSI Architectural Synthesis – Kluwer 1992.
  8. Nekoogar, Farzad - Timing Verification of Application Specific Integrated Circuits [ASIC'S] Prentice Hall 1999.
  9. Kropf, Thomas - Introduction Formal Hardware Verification – Springer, Berlin 2003.
  10. Gerald Weyerer, Manfred Goldemund - Testability of Electronic Circuits – Prentice Hall 1992.
  11. Bushnell, Michael L, Agrawal, Vishwani D - Essential of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits – Kluwer 2000.
  12. Shepherd, Peter - Integrated Circuit Design, Fabrication and Test – Mc Graw Hill 1996.