VSD 403L - ASIC Lab  
 

Indicative contents

  • Design, Synthesis, timing analysis and formal verification of combinational design
    1. Pipelined 8-bit Multiplier
    2. Adder / Subtractor
    3. ALU
    4. Signed Divider
  • Design, Synthesis, timing analysis and formal verification of
    1. Gray Counter
    2. LFSR
    3. Up/Down Counter
    4. CRC
    5. FIR Filter
  • Design, Synthesis, timing analysis and formal verification of FSM designs
    1. Sequence Detector
    2. Traffic Light Controller
  • Design, Synthesis, timing analysis and formal verification of hierarchical designs
    1. Ripple carry adders
    2. Wallace tree multipliers
  • Design, Synthesis, timing analysis and formal verification of complex circuits with multiple clock domains
    1. Asynchronous FIFO
    2. Real Time digital clock
  • Design, Synthesis, timing analysis and formal verification of memory designs
    1. Dual Port RAM
     

Module Resources

  • Books
    1. Smith, Michael John Sebastian - Application - Specific Integrated Circuits – Pearson 1997.
    2. Micheli, Giovanni - Synthesis and Optimization of Digital Circuits – Tata Mc Graw Hill 2005.
    3. Himanshu Bhatnagar - Advanced Asic Chip Synthesis Using Synopsys Design Compiler Physical and PrimeTime – Kluwer 2002.
    4. Pran Kurup, Pran, Abbasi, Taber - Logic Synthesis Using Synopsys – Kluwer 1997.
    5. Sabih Gerez - Algorithms for VLSI Design Automation – John Wiley 1998.
    6. Horspool, Nigel, Gorman, Peter - ASIC Handbook – Prentice Hall 2001.
    7. Gebotys, Catherine H, Elmasry, Mohamed - Optimal VLSI Architectural Synthesis – Kluwer 1992.
    8. Nekoogar, Farzad - Timing Verification of Application Specific Integrated Circuits [ASIC'S] Prentice Hall 1999.
    9. Kropf, Thomas - Introduction Formal Hardware Verification – Springer, Berlin 2003.
    10. Gerald Weyerer, Manfred Goldemund - Testability of Electronic Circuits – Prentice Hall 1992.
    11. Bushnell, Michael L, Agrawal, Vishwani D - Essential of Electronic Testing for Digital, Memory and Mixed Signal VLSI Circuits – Kluwer 2000.
    12. Shepherd, Peter - Integrated Circuit Design, Fabrication and Test – Mc Graw Hill 1996.
       
  • Laboratory

Software Tools / Hardware : • Synopsys Front end tools -  Design Compiler V-2004.06,  Prime Time X-2005.12,  Formality V-2004.06,  DFT V-2004.06,
• Cadence Front end tools  -  RTL Compiler 6.1,  Pearl Version 6.1 ,  LEC Version 6.1,
Lab Manuals : DC lab MSRSAS Manua, Primetime MSRSAS Tutorial, DFT MSRSAS Manual, RTL Compiler MSRSAS Manual